VHDL

VHSIC Hardware Description Language

VHDL or VHSIC Hardware Description Language, is commonly used as a design-entry language for FPGAs and ASICs in electronic design automation.

VHDL was originally developed at the behest of the US Department of Defense in order to document the behaviour of the ASICs that supplier companies were including in equipment. That is to say, VHDL was developed as a alternative to huge, byzantine manuals which are subject to implementation specific minutiae.

The idea of being able to simulate this behaviour was so obviously attractive that logic simulators were developed that could read the VHDL files. The next step was the development of logic synthesis tools that read the VHDL, and output a definition of the physical implementation of the circuit. Modern synthesis tools can extract RAM, counter, and arithmetic blocks out of the code, and implement them according to what user specifies. Thus, the same VHDL code could be synthezied differently for lowest cost, most power efficient, highest speed, etc

The initial version of VHDL, to standard IEEE 1076-1987, included a wide range of data types, including numerical (integer and real), logical (bit and boolean), character and time, plus arrays of bit called bit_vector and of character called string.

A problem not solved by this edition, however, was "multi-valued logic", where a signal's drive strength (none, weak or strong) and unknown values are also considered. This required IEEE standard 1164, which defined the 9-value std_logic.

The second issue of IEEE 1076, in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the character type to match the full 8-bit ASCII definition, added the xnor operator, etc.

More recently, the language has been extended by introducing signed and unsigned types to facilitate arithmetical operations; analog and mixed-signal circuit design extensions; VITAL (VHDL Initiative Towards ASIC Libraries); microwave circuit design extensions

VHDL has a syntax similar to Pascal and Ada, thus being a descendant of Algol. VHDL is case insensitive.

This page is linked from: Confluence   FPGA   Hardware description language   programmable logic device